1. Field of the Disclosure
The present disclosure relates generally to memory devices and, more particularly, to single-port memory devices.
2. Background of the Disclosure
The need to read and write simultaneously to a computer memory device is satisfied by dual-port memory devices; however, dual-port memory devices are relatively expensive compared to single-port memory devices. A single-port memory device, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), can either read or write during any specific time period, typically during a single clock cycle, but cannot read or write during a specific time period at the same time.
Other memory devices incorporate a single-port SRAM that utilizes separate read and write cycles from a clock. Other memory devices utilize a circuit with a dual port first-in and first-out (FIFO) memory stack, wherein the circuit includes a first and second bank and single-port RAMs to its data are written in alternation and, wherein each bank when not being written to is read from.
Other memory devices include a single-port memory which is used to store an image which can be read from and simultaneously written to. Separate read and write buffers communicate to an arbiter section, which in turn communicates with the single board memory.
Other memory devices simultaneously read and write data into a single-port RAM, wherein new data is stored in a corresponding new data address in a buffer, and a comparison is made of the new data address with a current read address. In the event that the read and write addresses are the same, the new data is stored at a modified address.
When two hosts from different clock regimes (i.e., clocks are asynchronous) want to access the same synchronous RAM, presently there are two architectures that may be utilized. The first architecture may utilize a dual-port synchronous RAM. Control logic needed for a dual-port synchronous RAM may be relatively simple, but the disadvantage of this architecture is that the dual-port synchronous RAM is bigger and more expensive than a single-port synchronous RAM. In addition, some manufacturers may not support a dual-port synchronous RAM in the end product.
Another architecture may utilize a single-port synchronous RAM wherein the single-port synchronous RAM is connected to a clock port to one host's clock. The other host's signals need to be synchronous to the first host's clock; then the synchronous control/data signals from both hosts would pass through an arbitration block, which decides which host would have the right to access the RAM. The problem of this architecture and method is that the clock connecting to the RAM would always be required to be on. Otherwise, if the first host's clock is turned off, the other host could not access the RAM. The other shortcoming of this architecture and method is the delay that would be introduced and the extra hardware that would be required by the synchronization and arbitration requirements.
What is needed is a system and method to accommodate asynchronous hosts that want to access the same RAM at the same time.